多周期CPU设计

`timescale 1ns / 1ps
module MultipleCPU(
	input CLK,
	input Reset,
	output [5:0] op,
	output [4:0] rs,
	output [4:0] rt,
	output [4:0] rd,
	output [15:0] immediate,
	output [31:0] ReadData1,
	output [31:0] ReadData2,
	output [31:0] WriteData,
	output [31:0] DataOut,
	output [31:0] currentAddress,
	output [31:0] newAddress,
	output [31:0] result,
	output PCWre
);
	wire [31:0] A,B;
	wire [31:0] currentAddress_4, extendImmediate, currentAddress_immediate, outAddress, ALUM2DR;
	wire [4:0] WriteReg;
	wire [25:0] address;
	wire zero,sign, ALUSrcA,ALUSrcB, ALUM2Reg, RegWre, WrRegData, InsMemRW, DataMemRW, IRWre;
	wire [1:0] ExtSel, PCSrc, RegOut;
	wire [2:0] ALUOp;
	wire [31:0] RegReadData1, RegReadData2, RegResult, RegDataOut;
	ControlUnit cu(CLK, Reset, op, zero,sign,PCWre, ALUSrcA, ALUSrcB, ALUM2Reg,
		RegWre, WrRegData, InsMemRW, DataMemRW, IRWre, ExtSel, PCSrc, RegOut, ALUOp);
	PC pc(CLK, Reset, PCWre, newAddress, currentAddress);
	InstructionMemory im(InsMemRW, currentAddress, CLK, IRWre, op, rs, rt, rd, immediate, address);
	RegisterFile rf(CLK, RegWre, rs, rt, WriteReg, WriteData, ReadData1, ReadData2);
	ALU alu(ALUOp, A, B, zero, result,sign);
	SignZeroExtend sze(ExtSel, immediate, extendImmediate);
	DataMemory dm(DataMemRW, RegResult, RegReadData2, DataOut);
	PCjump pcj(currentAddress, address, outAddress);
	assign currentAddress_4 = currentAddress + 4;
	assign currentAddress_immediate = currentAddress_4 + (extendImmediate << 2);
	//线转寄存器
	WireToReg wtrA(CLK, 1, ReadData1, RegReadData1);
	WireToReg wtrB(CLK, 1, ReadData2, RegReadData2);
	WireToReg wtrALU(CLK, 1, result, RegResult);
	WireToReg wtrMEM(CLK, 1, DataOut, RegDataOut);
	//2路选择器
	MUX2L_32 mux2_1(WrRegData, currentAddress_4, ALUM2DR, WriteData);
	MUX2L_32 mux2_4(ALUSrcA, RegReadData1, RegReadData2, A);
	MUX2L_32 mux2_2(ALUSrcB, RegReadData2, extendImmediate, B);
	MUX2L_32 mux2_3(ALUM2Reg, result, RegDataOut, ALUM2DR);
	//4路选择器
	MUX4L_5 mux4_1(RegOut, 5'b11111, rt, rd, 5'b00000, WriteReg);
	MUX4L_32 mux4_2(PCSrc, currentAddress_4, currentAddress_immediate,
		ReadData1, outAddress, newAddress);

endmodule

`timescale 1ns / 1ps
module ControlUnit(
	input CLK,	//时钟
	input reset,	//重置信号
	input [5:0] op,	//op操作符
	input zero,	//ALU的zero输出
	input sign,
	output reg PCWre,	//(PC)PC是否更改，如果为0，PC不更改，另外，除D_Tri == 000状态之外，其余状态也不能改变PC的值。
	output reg ALUSrcA,
	output reg ALUSrcB,
	output reg ALUM2Reg,
	output reg RegWre,	//(RF)写使能信号，为1时，在时钟上升沿写入
	output reg WrRegData,	//2路选择器，判断数据写入是否为PC指令，如果为1，则不是，jar用到
	output reg InsMemRW,	//(IM)读写控制信号，1为写，0位读，固定为0
	output reg DataMemRW,	//(DM)数据存储器读写控制信号，为1写，为0读
	output reg IRWre,	//寄存器写使能，暂时没什么用，固定为1
	output reg[1:0] ExtSel,	//(EXT)控制补位，如果为1，进行符号扩展，如果为0，全补0
	output reg[1:0] PCSrc,	//4路选择器，选择PC指令来源
	output reg[1:0] RegOut,	//4路选择器，判断写寄存器地址的来源
	output reg[2:0] ALUOp	//(ALU)ALU操作控制
);
	parameter[2:0]
		_ADD=	3'b000,
		_SUB=	3'b001,
		_SLL=	3'b010,
		_OR=	3'b011,
		_AND=	3'b100,
		_SLTU=	3'b101,
		_SLT=	3'b110,
		_XOR=	3'b111,
		IF=	3'b000,	//3位D触发器，代表8个状态
		ID=	3'b001,
		EXELS=	3'b010,
		MEM=	3'b011,
		WBL=	3'b100,
		EXEBR=	3'b101,
		EXEAL=	3'b110,
		WBAL=	3'b111;
	parameter[5:0]
		ADD=	6'b000000,
		SUB=	6'b000001,
		ADDIU=	6'b000010,
		AND=	6'b010000,
		ANDI=	6'b010001,
		ORI=	6'b010010,
		XORI=	6'b010011,
		SLL=	6'b011000,
		SLTI=	6'b100110,
		SLT=	6'b100111,
		SW=	6'b110000,
		LW=	6'b110001,
		BEQ=	6'b110100,
		BNE=	6'b110101,
		BLTZ=	6'b110110,
		J=	6'b111000,
		JR=	6'b111001,
		JAL=	6'b111010,
		HALT=	6'b111111;
	reg[2:0] D_Tri;
	initial begin
		PCWre=0;
		ALUSrcB=0;
		ALUM2Reg=0;
		RegWre=0;
		WrRegData=0;
		//no change
		InsMemRW=0;
		DataMemRW=0;
		//no change
		IRWre=1;
		ExtSel=0;
		PCSrc=0;
		RegOut=0;
		ALUOp=0;
		D_Tri=0;
	end
	//D触发器变化，PS：为了避免竞争冒险，所有值变化改为下降沿触发
	//PCWre，RegWre和DataMemRW的变化影响很大，要在这里写
	always@(negedge CLK or posedge reset)begin
		if(reset)begin//重置属性
			D_Tri=IF;
			PCWre=0;
			RegWre=0;
		 end
		else begin
			case (D_Tri)
				//IF -> ID
				IF: begin
					D_Tri <= ID;
					//禁止写指令，寄存器，和内存
					PCWre=0;
					RegWre=0;
					DataMemRW=0;
				end
				//ID -> EXE
				ID:begin
					case (op)
						//如果是BEQ指令，跳到EXEBR
						BEQ, BNE, BLTZ:  D_Tri <= EXEBR;
						//如果是SW，LW指令，跳到EXELS
						SW, LW:  D_Tri <= EXELS;
						//如果是j，JAL，JR，HALT，跳到IF
						J, JAL, JR, HALT:begin
						   D_Tri=IF;
							//如果指令是HALT，禁止写指令
							if (op == HALT)  PCWre=0;
							else  PCWre=1;
							//如果指令是JAL，允许写寄存器
							if (op == JAL)  RegWre=1;
							else  RegWre=0;
						end
						//其他，跳到EXEAL
						default:  D_Tri=EXEAL;
					endcase
				 end
				//EXEAL -> WBAL
				EXEAL:begin
					D_Tri=WBAL;
					//允许写寄存器
					RegWre=1;
				end
				//EXELS -> MEM
				EXELS:begin
					D_Tri=MEM;
					//如果指令为SW，允许写内存
					if (op == SW)  DataMemRW=1;
				end
				//MEM -> WBL
				MEM:begin
					//如果指令为SW，MEM -> IF
					if (op == SW)begin
						D_Tri=IF;
						//允许写指令
						PCWre=1;
					end
					//如果指令为LW，MEM -> WBL
					else begin
						D_Tri=WBL;
						//允许写寄存器
						RegWre=1;
					end
				end
				//其他 -> IF
				default:begin
					D_Tri=IF;
					//允许写指令
					PCWre=1;
					//禁止写寄存器
					RegWre=0;
				end
			endcase
		end
	end
	always@(op or zero)begin//一般信号
		ALUSrcA=	op==SLL;
		ALUSrcB=	op==ADDIU||op==ANDI||op==ORI||op==XORI||op==SLTI||op==LW||op==SW||op==SLL;
		ALUM2Reg=	op==LW;
		WrRegData=	op!=JAL;	//2路选择器，判断数据写入是否为PC指令，如果为1，则不是，jar用到
		InsMemRW=	0;//(IM)读写控制信号，1为写，0位读，固定为0
		IRWre=	1;   //寄存器写使能，暂时没什么用，固定为1
		ExtSel=	op==SLL?2'b00:op==ANDI||op==XORI||op==ORI?2'b01:2'b10; //(EXT)控制补位，如果为1，进行符号扩展，如果为0，全补0
		PCSrc=	op==J||op==JAL?2'b11:
				op==JR?2'b10:
				(op==BEQ&&zero==1)||(op==BNE&&zero==0)||(op==BLTZ&&sign==1)?2'b01:
				2'b00;  //4路选择器，选择PC指令来源
		RegOut=	op==JAL?2'b00:
				op==ADD||op==SUB||op==AND||op==SLT||op==SLL?2'b10:
				2'b01; //4路选择器，判断写寄存器地址的来源
		ALUOp=	op==SUB||op==BEQ||op==BNE||op==BLTZ?_SUB:
				op==SLL?_SLL:
				op==ORI?_OR:
				op==ANDI||op==AND?_AND:
				op==SLT||op==SLTI?_SLT:
				op==XORI?_XOR:_ADD;	//(ALU)ALU操作控制
	 end
endmodule

`timescale 1ns / 1ps
module WireToReg(
	input CLK,
	input RW, //未用
	input [31:0]data1,
	output reg[31:0]data2
);
	integer i;
	always@(negedge CLK)begin
		for (i = 0; i < 32; i = i + 1)data2[i] = data1[i];
	end
endmodule

`timescale 1ns / 1ps
module ALU(
	input[2:0] ALUOp,
	input[31:0] A,
	input[31:0] B,
	output zero,
	output reg[31:0] result,
	output sign
);
	parameter _ADD=	3'b000;
	parameter _SUB=	3'b001;
	parameter _SLL=	3'b010;
	parameter _OR=	3'b011;
	parameter _AND=	3'b100;
	parameter _SLTU=	3'b101;
	parameter _SLT=	3'b110;
	parameter _XOR=	3'b111;
	assign zero=	result==0;
	assign sign=	result[31];
	always@(*)begin
		case(ALUOp)
		_ADD:	result=	A+B;
		_SUB:	result=	A-B;
		_SLL:	result=	A<<B;
		_OR:	result=	A|B;
		_AND:	result=	A&B;
		_SLTU:	result=	A<B;
		_SLT:	result=	A[31]!=B[31]?A[31]>B[31]:A<B;
		_XOR:	result=	A^B;
		default:	result=	0;
		endcase
	end
endmodule

`timescale 1ns / 1ps
module DataMemory(
	input DataMemRW,
	input [31:0] DAddr,
	input [31:0] DataIn,
	output reg [31:0] DataOut
);
	reg [7:0] memory[0:255];
	integer i;
	initial  begin
		for (i = 0; i < 256; i = i + 1)memory[i] <= 0;
		for (i = 0; i < 32; i = i + 1)DataOut[i] <= 0;
	end
	always@(DAddr or DataMemRW)begin
		if (DataMemRW)begin
		   memory[DAddr] <= DataIn[31:24];
			memory[DAddr + 1] <= DataIn[23:16];
			memory[DAddr + 2] <= DataIn[15:8];
			memory[DAddr + 3] <= DataIn[7:0];
		end
		else begin
		   DataOut[31:24] <= memory[DAddr];
			DataOut[23:16] <= memory[DAddr + 1];
			DataOut[15:8] <= memory[DAddr + 2];
			DataOut[7:0] <= memory[DAddr + 3];
		end
	end
endmodule

`timescale 1ns / 1ps
module InstructionMemory(
	input InsMemRW,	//读写控制信号，1为写，0位读
	input [31:0] IAddr,	//指令地址输入入口
	//input IDataIn,	//没用到
	input CLK,	//时钟信号
	input IRWre,	//输出寄存器写使能
	output reg[5:0] op,
	output reg[4:0] rs,
	output reg[4:0] rt,
	output reg[4:0] rd,
	output reg[15:0] immediate,	//指令代码分时段输出
	output reg[25:0] address
);
	reg[7:0] mem[0:255];	//新建一个256位的数组用于储存指令
	initial begin
		//初始化
		op <= 0;
		rs <= 0;
		rt <= 0;
		rd <= 0;
		immediate <= 0;
		address <= 0;
		$readmemb("C:/Users/wukan/Documents/VIVADO/MultipleCPU/input.txt",mem);
	end
	//从地址取值，然后输出
	always@(posedge CLK or posedge IRWre)begin
		if (IRWre == 1)begin
			op = mem[IAddr][7:2];
			rs[4:3] = mem[IAddr][1:0];
			rs[2:0] = mem[IAddr + 1][7:5];
			rt = mem[IAddr + 1][4:0];
			rd = mem[IAddr + 2][7:3];
			immediate[15:8] = mem[IAddr + 2];
			immediate[7:0] = mem[IAddr + 3];
			//地址赋值
			address[25:21] = rs;
			address[20:16] = rt;
			address[15:0] = immediate;
		end
	end
endmodule

`timescale 1ns / 1ps
module MUX2L_32(
	input control,
	input [31:0] in0,
	input [31:0] in1,
	output [31:0] out
);
	assign out = control ? in1 : in0;
endmodule

`timescale 1ns / 1ps
module MUX4L_32(
	input [1:0]control,
	input [31:0] in00,
	input [31:0] in01,
	input [31:0] in10,
	input [31:0] in11,
	output [31:0] out
);
	assign out = control[0] ? (control[1] ? in11 : in01) : (control[1] ? in10 : in00);
endmodule

`timescale 1ns / 1ps
module MUX4L_5(
	input [1:0] control,
	input [4:0] in00,
	input [4:0] in01,
	input [4:0] in10,
	input [4:0] in11,
	output [4:0] out
);
	assign out = control[0] ? (control[1] ? in11 : in01) : (control[1] ? in10 : in00);
endmodule

`timescale 1ns / 1ps
module PC(
	input CLK,	//时钟
	input Reset,	//重置信号
	input PCWre,	//PC是否更改，如果为0，PC不更改
	input [31:0] newAddress,	//新指令
	output reg[31:0] currentAddress	//当前指令
);
	initial begin
		currentAddress <= 0;  //非阻塞赋值
	end
	always@(posedge CLK or posedge Reset)begin
		if (Reset == 1)  currentAddress <= 0;  //如果重置，赋值为0
		else begin
			if (PCWre)  currentAddress <= newAddress;
			else  currentAddress <= currentAddress;
		end
	end
endmodule

`timescale 1ns / 1ps
module PCjump(
	input [31:0] PC0,	//指令
	input [25:0] inAddress,	//输入地址
	output [31:0] outAddress	//输出地址(指令)
);
	assign outAddress[31:28] = PC0[31:28];
	assign outAddress[27:2] = inAddress;
	assign outAddress[1:0] = 2'b00;
endmodule

`timescale 1ns / 1ps
module RegisterFile(
	input CLK,	//时钟
	input RegWre,	//写使能信号，为1时，在时钟上升沿写入
	input [4:0] rs,	//rs寄存器地址输入端口
	input [4:0] rt,	//rt寄存器地址输入端口
	input [4:0] WriteReg,	//将数据写入的寄存器端口，其地址来源rt或rd字段
	input [31:0] WriteData,	//写入寄存器的数据输入端口
	output [31:0] ReadData1,	//rs数据输出端口
	output [31:0] ReadData2	//rt数据输出端口
);
	reg [31:0] register[0:31];  //新建32个寄存器，用于操作
	//初始时，将32个寄存器和ReadData全部赋值为0
	integer i;
	initial begin
		for(i = 0; i < 32; i = i + 1)  register[i] <= 0;
	end
	//直接读寄存器
	assign ReadData1 = register[rs];
	assign ReadData2 = register[rt];
	//接受信号并读寄存器
	always@(posedge CLK)begin
		//如果寄存器不为0，并且RegWre为真，写入数据
		if (RegWre && WriteReg != 0)  register[WriteReg] = WriteData;
	end
endmodule

`timescale 1ns / 1ps
module SignZeroExtend(
	input [1:0]ExtSel,	//控制补位，如果为1X，进行符号扩展；01，immediate全补0；00，sa全补0
	input [15:0] immediate,	//16位立即数
	output [31:0] extendImmediate	//输出的32位立即数
);
	assign extendImmediate[4:0] = (ExtSel == 2'b00) ? immediate[10:6] : immediate[4:0];
	assign extendImmediate[15:5] = (ExtSel == 2'b00) ? 3'b00000000000 : immediate[15:5];
	assign extendImmediate[31:16] = (ExtSel == 2'b10) ? (immediate[15] ? 16'hffff : 16'h0000) : 16'h0000;
endmodule

`timescale 1ns / 1ps
module Sim;
	reg CLK;	//时钟信号
	reg Reset;	//置零信号
	MultipleCPU mcpu(CLK,Reset);
	initial begin
		CLK=	0;
		Reset=	1;	//刚开始设置pc为0
		#50;	//等待Reset完成
		CLK=	!CLK;	//下降沿，使PC先清零
		#50;
		Reset=	0;	//清除保持信号
	  	forever #50 begin	//产生时钟信号，周期为50s
			CLK=	!CLK;
		end
	end
endmodule

`timescale 1ns / 1ps
module Basys3(
	input CLK,
	input[1:0] SW,	//选择输出信号
	input Reset,	//重置按钮
	input Button,	//单脉冲
	output reg[3:0] AN,	//数码管位选择信号
	output[7:0] Out	//数码管输入信号
);
	parameter T1MS=	100000;
	reg[16:0] showCounter;
	wire[31:0] ALU_Out;	//ALU的result输出值
	wire[31:0] CurPC;
	wire[31:0] WriteData;	//DB总线值
	wire[31:0] Reg1Out;	//寄存器组rs寄存器的值
	wire[31:0] Reg2Out;	//寄存器组rt寄存器的值
	wire[31:0] DataOut;
	wire[31:0] instcode;
	wire myCLK;
	reg[3:0] store;	//记录当前要显示位的值
	wire[31:0] newAddress;

	MultipleCPU mcpu(myCLK,Reset,instcode[31:26],instcode[25:21],instcode[20:16],instcode[15:11],instcode[15:0],Reg1Out,Reg2Out,WriteData,DataOut,CurPC,newAddress,ALU_Out);
	Debounce debounce(CLK,Button,myCLK);

	initial begin
		showCounter<=	0;
		AN<=	4'b0111;
	end
	always@(posedge CLK)
		begin
		if(Reset==1)begin
		  showCounter<=	0;
		  AN<=	4'b0000;
		end else begin
			showCounter<=	showCounter+1;
			if(showCounter==T1MS)
				begin
					showCounter<=	0;
					case(AN)
						4'b1110:	begin
							AN<=	4'b1101;
						end
						4'b1101:	begin
							AN<=	4'b1011;
						end
						4'b1011:	begin
							AN<=	4'b0111;
						end
						4'b0111:	begin
							AN<=	4'b1110;
						end
						4'b0000:	begin
							AN<=	4'b0111;
					   end
					endcase
				end
			end
		end
	SegLED led(store,Reset,Out);
	always@(myCLK)begin
	   case(AN)
			4'b1110:	begin
				case(SW)
					2'b00:	store<=	newAddress[3:0];
					2'b01:	store<=	Reg1Out[3:0];
					2'b10:	store<=	Reg2Out[3:0];
					2'b11:	store<=	WriteData[3:0];
				endcase
			end
			4'b1101:	begin
				case(SW)
					2'b00:	store<=	newAddress[7:4];
					2'b01:	store<=	Reg1Out[7:4];
					2'b10:	store<=	Reg2Out[7:4];
					2'b11:	store<=	WriteData[7:4];
				endcase
			end
			4'b1011:	begin
				case(SW)
					2'b00:	store<=	CurPC[3:0];
					2'b01:	store<=	instcode[24:21];
					2'b10:	store<=	instcode[19:16];
					2'b11:	store<=	ALU_Out[3:0];
				endcase
			end
			4'b0111 : begin
				case(SW)
					2'b00:	store<=	CurPC[7:4];
					2'b01:	store<=	{3'b000,instcode[25]};
					2'b10:	store<=	{3'b000,instcode[20]};
					2'b11:	store<=	ALU_Out[7:4];
				endcase
			end
		endcase
	end
endmodule

`timescale 1ns / 1ps
module Debounce(clk,key_in,key_out);
    parameter SAMPLE_TIME = 5000;
    input clk;
    input key_in;
    output key_out;
    reg [21:0] count_low;
    reg [21:0] count_high;
    reg key_out_reg;
    always @(posedge clk)
    if(key_in ==1'b0)
        count_low <= count_low + 1;
    else
        count_low <= 0;
    always @(posedge clk)
        if(key_in ==1'b1)
            count_high <= count_high + 1;
        else
            count_high <= 0;
    always @(posedge clk)
        if(count_high == SAMPLE_TIME)
            key_out_reg <= 1;
        else if(count_low == SAMPLE_TIME)
            key_out_reg <= 0;
    assign key_out = !key_out_reg;
endmodule

`timescale 1ns / 1ps
module SegLED(
	input[3:0] Store,
	input Reset,
	output reg[7:0] Out
);
	always@(Store or Reset)begin
		begin
			case(Store)
				4'b0000:	Out=	8'b00000011;	//0
				4'b0001:	Out=	8'b10011111;	//1
				4'b0010:	Out=	8'b00100101;	//2
				4'b0011:	Out=	8'b00001101;	//3
				4'b0100:	Out=	8'b10011001;	//4
				4'b0101:	Out=	8'b01001001;	//5
				4'b0110:	Out=	8'b01000001;	//6
				4'b0111:	Out=	8'b00011111;	//7
				4'b1000:	Out=	8'b00000001;	//8
				4'b1001:	Out=	8'b00001001;	//9
				4'b1010:	Out=	8'b00010001;	//A
				4'b1011:	Out=	8'b11000001;	//b
				4'b1100:	Out=	8'b01100011;	//C
				4'b1101:	Out=	8'b10000101;	//d
				4'b1110:	Out=	8'b01100001;	//E
				4'b1111:	Out=	8'b01110001;	//F
				default:	Out=	8'b00000000;	//all light
			endcase
		end
	end
endmodule